• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    In order to prevent the core phenomenon after embedding the oxide film in the shallow trench for semiconductor device isolation, a pad oxide film and a nitride film are formed on the silicon wafer, and the nitride film and the pad oxide film are patterned to form a moat pattern, and the silicon is used as a mask. After forming the trench by mort etching the wafer, the silicon wafer is thermally oxidized to form a liner oxide film on the inner wall of the trench. And, 500 ℃ to high temperature at a reaction temperature TEOS / O of 550 ℃ 3 atmospheric pressure chemical vapor deposition of a thin NSG film is deposited to a thickness of less than 500Å, and at low temperatures, the reaction temperature of 400 ℃ to 430 ℃ TEOS / O 3 atmospheric pressure chemical vapor deposition The NSG film is deposited to fully fill the trench. Therefore, it is possible to prevent the seam phenomenon occurring after embedding the NSG film in the trench, thereby minimizing damage during subsequent chemical mechanical polishing, wet etching, and hydrofluoric acid degradation, thereby stably preventing current leakage, an electrical characteristic of the integrated circuit device. It can be reduced to improve the yield of the semiconductor device manufacturing process, and improve the reliability of the semiconductor device.
    公开号:KR20000061332A
    申请号:KR1019990010292
    申请日:1999-03-25
    公开日:2000-10-16
    发明作者:백승룡；고한석
    申请人:황인길；아남반도체 주식회사；
    IPC主号:
    专利说明:

    Shallow trench manufacturing method for semiconductor device isolation {SHALLOW TRENCH MANUFACTURING METHOD FOR ISOLATING SEMICONDUCTOR DEVICES}
    BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a process for manufacturing a semiconductor device, and more particularly, to a method of manufacturing a shallow trench for electrically isolating a semiconductor device from a device during a semiconductor device manufacturing process.
    In general, a method of separating a semiconductor device has been used a local oxidation of silion (LOCOS) device separation method using a nitride film as a selective oxidation method.
    Since the LOCOS device isolation method thermally oxidizes the silicon wafer itself using a nitride film as a mask, the process is simple and there is an advantage that the device stress problem of the oxide film is small, and the resulting oxide film quality is good.
    However, when the LOCOS device isolation method is used, the area of the device isolation region is large, thereby limiting device miniaturization and generating bird's beaks.
    In order to overcome this, a trench trench isolation (STI) technique is an alternative to the LOCOS isolation scheme. In trench device isolation, since trenches are made in silicon wafers to insulate the insulating material, the area occupied by the device isolation region is small, which is advantageous for miniaturization of devices.
    Next, a method of manufacturing a shallow trench for separating a conventional semiconductor device will be described with reference to FIGS. 1A to 1C.
    First, as shown in FIG. 1A, the silicon wafer 1 is thermally oxidized to grow the pad oxide film 2, and the nitride film 3 is deposited by chemical vapor deposition (CVD) thereon.
    Next, as shown in FIG. 1B, the nitride film 3 and the pad oxide film 2 are used to distinguish the active region in which the semiconductor device is to be formed and the field region in which the semiconductor device isolation region is to be formed. ) To form a moat pattern, and then the silicon wafer 1 exposed by the mask as a mask is mot-etched to form a shallow trench in the semiconductor device isolation region. Then, the silicon wafer 1 is thermally oxidized to grow the liner oxide film 4 on the inner wall of the trench. At this time, the liner oxide layer 4 serves as a glue layer to the material deposited in a subsequent process while compensating for damage caused by the mort etching of the silicon wafer 1.
    Next, as shown in FIG. 1C, TEOS and ozone (organometallic liquid source chemicals) under 760 Torr process pressure are used by TEOS (tetraethylorthosilicate) / O 3 atmospheric pressure chemical vapor deposition (APCVD) method. An oxide film is deposited by thermal chemical vapor deposition of O 3 ) to complete device isolation between the active region and the field region.
    This conventional method does not overcome the surface sensitivity effects due to the chemical composition and surface potential differences of the underlying dielectric at the wafer surface, which is pointed out as a general disadvantage of TEOS / O 3 atmospheric pressure chemical vapor deposition films. . Accordingly, a polymer filament phenomenon (6 in FIG. 1C) after deposition of the oxide film occurs in the shallow trench region due to the sensitive surface sensitivity effect on the wafer surface. That is, the liner oxide film generally has an unstable potential on its surface. This is due to the potential difference between the pattern densities during the etching of the mort for forming trenches in manufacturing. If the trench is buried in this characteristic, the characteristics of the atmospheric chemical vapor deposition film affect the flowability on the surface, causing seam. In the atmospheric atmospheric chemical vapor deposition TEOS / O 3 process, due to the potential difference remaining on the lower film type and the trench curvature boundary surface in the shallow trench region and the conformal nature of each film laminated during the trench filling It is a thin line that appears.
    These seams are then damaged during chemical mechanical polishing (CMP) to planarize shallow trenches, wet etching to remove nitride, and hydrofluoric acid (HF) deglaze to open seam gaps resulting in current Leakage causes a great influence on the electrical reliability of the integrated circuit device.
    The present invention has been made to solve such a problem, and an object thereof is to prevent a core phenomenon that occurs after embedding an oxide film in a shallow trench for semiconductor device isolation.
    1A to 1C are cross-sectional views of silicon wafers schematically illustrating a process of manufacturing a shallow trench for semiconductor device isolation according to a conventional method;
    2A-2D are cross-sectional views of silicon wafers schematically illustrating a process of manufacturing a shallow trench for semiconductor device isolation in accordance with the present invention.
    In order to achieve the above object, the present invention is to deposit a thin NSG film by TEOS / O 3 atmospheric pressure chemical vapor deposition to decompose TEOS under an ozone concentration of 760 Torr, 130g / m 3 to 135g / m 3 to purchase a trench After the thin deposition of the NSG film to the lower layer at a high temperature reaction temperature, the NSG film is deposited at a low temperature reaction temperature to completely fill the trench.
    It is preferable to make the NSG film | membrane by the high temperature reaction temperature mentioned above in thickness below 500 kPa.
    In addition, it is preferable that the high temperature reaction temperature is 500 ° C to 550 ° C, and the low temperature reaction temperature is 400 ° C to 430 ° C.
    Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
    2A-2D are cross-sectional views of silicon wafers schematically illustrating a process of manufacturing a shallow trench for semiconductor device isolation in accordance with the present invention.
    First, as shown in FIG. 2A, the silicon wafer 11 is thermally oxidized to grow the pad oxide film 12, and the nitride film 13 is deposited by chemical vapor deposition on the silicon wafer 11.
    Next, as shown in FIG. 2B, the nitride layer 13 and the pad oxide layer 12 are patterned to form a mort pattern to distinguish the active region where the semiconductor element is to be formed and the field region where the semiconductor element isolation region is to be formed. Then, the silicon wafer 11 exposed by the mask of the mort pattern is mort-etched to form a shallow trench in the semiconductor device isolation region. The silicon wafer 11 is thermally oxidized to form a liner oxide film 14 on the inner wall of the trench. In this case, the liner oxide layer 14 compensates for the damage caused by the mort etching of the silicon wafer 11 and serves as a glue layer for the material deposited in a subsequent process.
    Next, a non-doped silicate glass (NSG) thin film is deposited by controlling the temperature at multiple temperatures by TEOS / O 3 atmospheric chemical vapor deposition to fill the trenches, thereby completing device isolation between the active and field regions.
    At this time, when depositing a non-doped silicate glass (NSG) thin film by TEOS / O 3 atmospheric pressure chemical vapor deposition method, as shown in Figure 2c, first, 760 Torr, organometallic liquid at 130g / m 3 to 135g / m 3 ozone concentration When the TEOS, which is the source chemical, is decomposed, the reaction temperature is adjusted to about 500 ° C. to about 550 ° C. to deposit the oxide film 15 as a thin NSG film with a thickness of 500 mW or less. At this time, the high temperature reaction temperature (about 500 ° C to 550 ° C) actively interacts with the oxidant (O 2 / O 3 ) flow that determines the active gas composition in the chamber during the reaction, so that the liner oxide film 14 of the trench inner wall 14 The oxide film 15 can be obtained in which the surface charge effect is alleviated between the interface with and the surface potential is substantially neutralized. The oxide film 15 thus obtained serves as an excellent wet layer that mitigates the surface sensitivity according to the chemical composition of the lower dielectric liner oxide film 14 itself. This is because the gaps between the grids fill each other.
    Then, as shown in Figure 2d, 400 ℃ to 430 ℃ of the organometallic liquid source chemical TEOS at 760 Torr, 130g / m 3 to 135g / m 3 ozone concentration on the oxide film 15 to which the high temperature reaction temperature is applied The trench is completely embedded by depositing the oxide film 16 as the NSG film to which the low temperature reaction temperature is applied. Then, the oxide film 16 formed at a low temperature reaction temperature has a flowlike property and increases the fluidity of the oxide film 16 to form a stable oxide network structure, thereby obtaining a high quality film without core phenomenon.
    As such, the present invention can prevent seam phenomenon occurring after embedding an NSG film in a trench, thereby minimizing damage during subsequent chemical mechanical polishing, wet etching, and hydrofluoric acid degrading, thereby preventing current leakage, which is an electrical characteristic of an integrated circuit device. Can be stably reduced, so that the yield of the semiconductor device manufacturing process can be improved and the reliability of the semiconductor device can be improved.
    权利要求:
    Claims (5)
    [1" claim-type="Currently amended] Forming a pad oxide film and a nitride film on the silicon wafer, and patterning the nitride film and the pad oxide film to form a mort pattern;
    Forming a trench by mort etching a silicon wafer using the mort pattern as a mask;
    Thermally oxidizing the silicon wafer to form a liner oxide layer on the inner wall of the trench;
    Embedding an NSG film in the trench;
    The step of embedding an NSG film in the trench,
    Depositing a thin NSG film by TEOS / O 3 atmospheric chemical vapor deposition at a high temperature reaction temperature;
    And depositing an NSG film by TEOS / O 3 atmospheric pressure chemical vapor deposition at a low temperature reaction temperature to completely fill the trench.
    [2" claim-type="Currently amended] 2. The method of claim 1, wherein in the depositing a thin NSG film by TEOS / O 3 atmospheric chemical vapor deposition at the high temperature reaction temperature, the deposited NSG film has a thickness of 500 μm or less. Way.
    [3" claim-type="Currently amended] The method of claim 2, wherein the high temperature reaction temperature is 500 ℃ to 550 ℃ shallow trench manufacturing method for the isolation of the semiconductor device.
    [4" claim-type="Currently amended] The semiconductor device of claim 3, wherein in the depositing of the NSG film by TEOS / O 3 atmospheric pressure chemical vapor deposition at the low temperature reaction temperature to completely fill the trench, the low temperature reaction temperature is 400 ° C. to 430 ° C. 5. Shallow trench preparation method for separation.
    [5" claim-type="Currently amended] The NSG film according to any one of claims 1 to 4, wherein the NSG film by TEOS / O 3 atmospheric chemical vapor deposition is deposited by decomposing TEOS under an ozone concentration of 760 Torr and 130 g / m 3 to 135 g / m 3 . A shallow trench manufacturing method for isolating semiconductor devices.
    类似技术:
    公开号 | 公开日 | 专利标题
    US6683354B2|2004-01-27|Semiconductor device having trench isolation layer and a method of forming the same
    US5313094A|1994-05-17|Thermal dissipation of integrated circuits using diamond paths
    CN100424850C|2008-10-08|Method for producing shallow trench isolation structure and semiconductor structure
    US6191004B1|2001-02-20|Method of fabricating shallow trench isolation using high density plasma CVD
    KR100426484B1|2004-04-14|Flash memory cell and method of manufacturing the same
    US6187651B1|2001-02-13|Methods of forming trench isolation regions using preferred stress relieving layers and techniques to inhibit the occurrence of voids
    US6566229B2|2003-05-20|Method of forming an insulating layer in a trench isolation type semiconductor device
    KR100426483B1|2004-04-14|Method of manufacturing a flash memory cell
    US6914316B2|2005-07-05|Semiconductor trench isolation structure
    US6265302B1|2001-07-24|Partially recessed shallow trench isolation method for fabricating borderless contacts
    KR100253079B1|2000-04-15|Semiconductor element trench isolation method
    US6214698B1|2001-04-10|Shallow trench isolation methods employing gap filling doped silicon oxide dielectric layer
    TWI248639B|2006-02-01|Method of manufacturing a semiconductor device
    TW536775B|2003-06-11|Manufacturing method of shallow trench isolation structure
    TWI255012B|2006-05-11|Method of manufacturing a flash memory cell
    KR100546852B1|2006-01-25|Method For Manufacturing Semiconductor Devices
    US6277706B1|2001-08-21|Method of manufacturing isolation trenches using silicon nitride liner
    JP2957169B2|1999-10-04|Method for forming device isolation layer of semiconductor device
    US6875670B2|2005-04-05|Trench isolation method
    JP4592340B2|2010-12-01|Manufacturing method of semiconductor device
    KR100406179B1|2003-11-17|Method of forming a self aligned floating gate in flash memory cell
    KR100677766B1|2007-02-05|Semiconductor device with trench type isolation and method for making the same
    KR100543455B1|2006-01-23|Method for forming trench isolation in semiconductor device
    US7858492B2|2010-12-28|Method of filling a trench and method of forming an isolating layer structure using the same
    EP1026740A2|2000-08-09|Formation of isolation layer over trench capacitor
    同族专利:
    公开号 | 公开日
    KR100315445B1|2001-11-28|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1999-03-25|Application filed by 황인길, 아남반도체 주식회사
    1999-03-25|Priority to KR1019990010292A
    2000-10-16|Publication of KR20000061332A
    2001-11-28|Application granted
    2001-11-28|Publication of KR100315445B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019990010292A|KR100315445B1|1999-03-25|1999-03-25|Shallow trench manufacturing method for isolating semiconductor devices|
    [返回顶部]